Field
The disclosed technology relates to semiconductor manufacturing, and particularly to a method of depositing a tungsten (W) layer on a substrate with improved adhesion and filling behavior.
Description of the Related Technology
As the feature size of complementary metal oxide semiconductor (CMOS) devices scales down, gate oxide thickness approaches atomic distances. Due to the tunneling effect, increased gate leakage current, reduced reliability and the like become significant problems. Thus, the conventional gate dielectric material of SiO2 cannot meet the requirement for further scaling of CMOS devices. Beyond 45 nm node process technology, it may be necessary to replace SiO2 with gate dielectrics with a high dielectric constant (high-K). However, conventional polysilicon gates may not be compatible with high-K material, leading to problems including increased threshold voltage (Vt), and significant interfacial reaction during annealing. Replacing polysilicon gates with metal gates may reduce gate depletion and boron penetration which are inherent to polysilicon gates.
High-K gates may be fabricated with either gate-first processes or gate-last processes. Gate-first processes are similar to conventional SiO2/polysilicon gate processes. In gate-first processes, gate dielectrics and metal gates are formed prior to forming drain and source regions. In contrast, in gate-last processes, sacrificial gates, sacrificial gate dielectric layers, source and drain regions, and interlayer dielectric layers are formed first. Then, sacrificial gates are removed and gates are re-formed.
Gate-first processes may anneal the source and drain at high temperatures that adversely impact some gate materials. As a result, the choice of gate materials is constrained for CMOS devices fabricated using these processes. An advantage of gate-last processes is that the gate material need not undergo annealing at high temperature. As a result, a greater variety of materials can be used to fabricate CMOS gates with gate-last processes. Companies can employ gate-last processes to develop and manufacture CMOS devices with small feature sizes, such as 45 nm or less.
Aluminum (Al) or tungsten (W) may be utilized for the gate electrode in gate-last processes. Intel reported a chip process of 45 nm utilizing AI as the material for the gate electrode. Since a planarization process follows the process of filling the metal electrode, and it is difficult to control the planarization process for aluminum in large-scale production, tungsten (W) may be a candidate gate material.
For gate-last processes, filling the gate material is implemented after removing the sacrificial gate, and thus the requirement for the filling behavior of the gate material is strict. Further, beyond 22 nm node process technology, the space for gate filling becomes smaller. As a result, conventional chemical vapor deposition (CVD) method may not meet the requirements for filling tungsten. Instead, atomic layer deposition (ALD) manufactured by a B2H6 source may be used to meet sheet resistance and filling behavior requirements for tungsten for metal gates.
However, since the B2H6 base ALD W film has poor adhesion, it may crack in the subsequent metal planarization process and to delaminate from a barrier layer of TiN, which adversely impacts yield.